1. Field of the Invention
This invention generally relates to integrated circuits (ICs) and, more particularly, to a surface mount emissive element, and an emissive display made using the surface mount emissive elements.
2. Description of the Related Art
The current competing technologies for large area display are liquid crystal display (LCD), organic light emitting device (OLED) display, and more recently, inorganic LED display. The weaknesses of LCD, which the current disclosure directly addresses, are 1) low efficiency where only about 5% of the light generated by the backlight is seen as an image by the user, and 2) low dynamic range because the LC material cannot completely block light to produce a black pixel. The weaknesses of OLED display are poor reliability and low efficiency (˜5% QE) of the blue OLED material. The use of inorganic micro-LEDs (uLEDs) in a display would provide a very high efficiency because the display would not use color filters and polarizers to absorb light. As used herein, a uLED is an LED with a diameter or cross-sectional area of 100 microns or less. The inorganic uLED display would have very high contrast because black pixels are set to emit no light. For an inorganic uLED display, blue gallium nitride (GaN) LEDs would be 35-40% efficient, with a reliability of over 50,000 hours, as has been established in general lighting. Sony has developed a passive matrix of uLEDs arranged in a display array using a pick and place system. However, since large displays require millions of LEDs, displays made by this process are time and cost prohibitive compared to other technologies.
The fluidic transfer of microfabricated electronic devices, optoelectronic devices, and sub-systems from a donor substrate/wafer to a large area and/or unconventional substrate provides a new opportunity to extend the application range of electronic and optoelectronic devices. For example, display pixel size LED micro structures, such as rods, fins or disks, can be first fabricated on small size wafers and then be transferred to large panel glass substrate to make a direct emitting display requiring no backlighting.
Conventional transfer techniques such as inkjet printing or robotic pick-and-place work reasonable well in certain particular applications. However, these conventional techniques are either not cost effective or so poor in yield that they cannot be applied to directly transfer LED micro structures.
There are three major processes in the fabrication of inorganic uLED disks for use in direct emission displays. These processes are: uLED disk fabrication; uLED disk distribution onto a transparent substrate; and, uLED disk interconnection. Since a fluidic assembly process distributes uLED disks randomly inside transparent substrate placement wells, it makes conventional IC style contact hole opening/metal interconnection design extremely challenging. Extra tolerances are required in the (opaque) interconnections to address this random distribution, resulting in a substantial loss in the emission area fill factor. Further, the complexity required to make these connections results in either a poor yield and/or high cost.
FIGS. 1A and 1B are plan views of a top-contact LED disk located in a substrate well (prior art). In FIG. 1A, Dd denotes the diameter of the LED (e.g., GaN) disk, Dc denotes the diameter of the micro-cavity or well into which the uLED disk has been distributed, and Dp denotes the diameter of the p-doped GaN (p-GaN) area, assuming the p-GaN is formed on the top of the disk. Area 100 is the n-GaN contact, where the p-GaN and MQW have been removed by a reactive ion etch (RIE). The inner circular area 102 is the full LED stack with p-GaN on top. A layer of nickel oxide (NiOx)/indium tin oxide (ITO) may be formed on the surface of area 102. In considering typical photolithography misalignment tolerances (up to 2 microns (μm)), the circular area 102 is off the GaN disk center by 2 μm. Since only the area 102 can emit light, the emission area fill factor is only about 70.6%. Nearly 30% of emission area is lost due to the n-GaN opening 100.
FIG. 1B shows the working area for anode end connection 104 (Dpc). Connections made outside of the 24 μm diameter area 104 are likely to result in either a short circuit or open circuit. Conventional metal interconnection to the n-GaN area 100 further reduces the emission area fill factor. Only 31.4% area of the GaN disk will emit light in this example.
FIG. 2 is a partial cross-sectional view of a bottom cathode contact architecture (prior art). This option avoids the significant emission area fill factor loss associated with a conventional top-contact LED disk. A bottom interconnection electrode 200 is first evaporated and patterned on a substrate 202, followed by micro-cavity (well) 204 formation. A thin layer of low melting temperature metal 206 is then coated on the bottom electrode surface inside the micro-cavity 204. The GaN disk 208 (n-GaN 210/p-GaN 212) is then distributed into the micro-cavity 204. After interlayer dielectric film 214 patterning, the top interconnection electrode 216 is evaporated and patterned to complete the whole process flow.
The process flow described by FIG. 2 is relatively simple. The front-side emission area fill factor can possible reach a maximum of 85% with a carefully selected top metal wiring design. Major challenges of this flow include the bottom contact yield, uniformity, reliability and repeatability, and the tradeoff between the bottom contact yield and the bottom electrode area if a backside emission opening is needed.
It would be advantageous if large emissive displays could be efficiently fabricated using a fluidic assembly process, through the employment of surface mount emissive elements.